This invention relates to nonvolatile semiconductor memory devices, more particularly, to an electrically-erasable, electrically-programmable ROM (read-only-memory) of the floating-gate type and to a method for making such a device.
EPROMs, or electrically-programmable ROMs, are nonvolatile field-effect devices with a floating-gate structure. In general, an EPROM floating gate is programmed by applying proper voltages to the source, drain and control gate of each cell, causing high current through the source-drain path and charging of the floating gate by hot electrons. The EPROM type of device is usually erased by ultraviolet light, which requires a device package having a quartz window above the semiconductor chip. Packages of this type are expensive in comparison with the plastic packages ordinarily used for other memory devices such as DRAMs (dynamic-random-access-memories). For this reason, EPROMs are generally more expensive than plastic-packaged devices. EPROM devices of this type, and methods of manufacture, are disclosed in U.S. Pat. Nos. 3,984,822; 4,142,926; 4,258,466; 4,376,947; 4,326,33I; 4,313,362; 4,373,248; or 4,750,24; for example.
EEPROMs, or electrically-erasable, electrically-programmable ROMs, have been manufactured by various processes, and usually require much larger cell sizes than standard EPROMs. The structures and the manufacturing processes are usually more complex. EEPROM arrays can be mounted in opaque plastic packages that reduce the packaging cost. Nevertheless, EEPROM arrays have been more expensive on a per-bit basis, in comparison with EPROM arrays, due to larger cell size and to more complex manufacturing processes.
As compared to EPROM arrays, EEPROM arrays require a wider range of voltages applied to bitlines for the purposes of programming, reading and erasing. Because the bitlines are connected to many cells in the array other than the cell being programmed, read, or erased, the wider range of voltages increases the possibility that one or more of the other cells will be inadvertently programmed or erased. The problem is particularly present in so-called "virtual-ground" arrays such as that disclosed in U.S. Pat. No. 4,281,397.
Flash EEPROMs have the advantage of smaller cell size in comparison with standard EEPROMs because the cells are not erased individually. Instead, the array of cells is erased in bulk.
Currently available flash EEPROMs require at least two external power supplies, one for programming and erasing and another for reading. Typically, a 12-volt power supply is used for programming and erasing and a 5-volt power supply is used during read operations. It is desirable, however, to employ a single relatively low-voltage supply for all of the programming, erasing and reading operations. For example, on-chip charge-pump techniques may be used to generate higher voltages from the 5-volt supply if the memory cells of the array are designed to be programmed and erased while drawing a relatively small current. In general, cells designed to use Fowler-Nordheim tunneling for programming and erasing require relatively small current in comparison to the current required when using hot-electron programming.
The EEPROMs disclosed in co-pending U.S. patent applications Ser. Nos. 07/219,528; 07/219,529, 07/219,530 and 07/360,558, now, all abandoned, provide greatly improved structures and methods for making cells having reduced size and ease of manufacture, resulting in a device requiring one relatively low-voltage (perhaps +5v) external power supply for the chip. The devices of those inventions use Fowler-Nordheim tunneling for erasure and for programming. However, the devices of those inventions require LOCOS isolation between bitlines. The LOCOS isolation in turn requires scarce additional space on an integrated circuit substrate.
There is need for a memory cell structure that can be downscaled in size and can be packaged in a less expensive opaque plastic package without requirement for space-consuming LOCOS isolation between bitlines of a memory array.